西安華芯半導(dǎo)體有限公司，創(chuàng)建于2004年初，原為德國英飛凌存儲(chǔ)器事業(yè)部，2006年成為奇夢達(dá)科技有限公司的西安研發(fā)中心。2009年5月被浪潮集團(tuán)山東華芯半導(dǎo)體收購，更名并轉(zhuǎn)制成為國有控股的獨(dú)立公司。公司擁有國內(nèi)、世界同步的集成電路產(chǎn)品設(shè)計(jì)開發(fā)能力，擁有完整先進(jìn)的集成電路設(shè)計(jì)軟硬件平臺以及投資超過一千多萬美元的測試中心。公司現(xiàn)有員工近兩百人，其中包括10名外籍專家、海外留學(xué)歸國人員和國家“”專家，具有碩士博士學(xué)位人員超過75%。
公司的主營業(yè)務(wù)是自有品牌存儲(chǔ)器產(chǎn)品開發(fā)以及先進(jìn)集成電路設(shè)計(jì)測試服務(wù)。華芯自有品牌大容量DRAM芯片及內(nèi)存條，廣泛應(yīng)用于服務(wù)器、平板電腦、高清電視機(jī)頂盒以及工業(yè)控制等領(lǐng)域，產(chǎn)品也遠(yuǎn)銷到大陸外的韓國、歐洲、美國等地。基于世界先進(jìn)工藝的存儲(chǔ)器產(chǎn)品設(shè)計(jì)服務(wù)，已成功給包括日本和臺灣存儲(chǔ)器公司開發(fā)完成多款大容量高速DRAM產(chǎn)品，同時(shí)為國內(nèi)外多個(gè)客戶提供了快速準(zhǔn)確的存儲(chǔ)器測試和失效分析服務(wù)。西安華芯還承擔(dān)有國家“核高基”和“863”計(jì)劃等多個(gè)存儲(chǔ)器領(lǐng)域的研究課題和項(xiàng)目，2014年榮獲國家“國家規(guī)劃布局內(nèi)重點(diǎn)軟件企業(yè)和集成電路設(shè)計(jì)企業(yè)”。
另外，基于公司先進(jìn)豐富的集成電路設(shè)計(jì)測試經(jīng)驗(yàn)和完善嚴(yán)謹(jǐn)?shù)漠a(chǎn)品開發(fā)流程管理和質(zhì)量管理，西安華芯也長期給包括美國公司提供基于先進(jìn)工藝的數(shù)字電路設(shè)計(jì)服務(wù)。
我們提供先進(jìn)的設(shè)計(jì)開發(fā)環(huán)境，優(yōu)厚的薪酬待遇，完善的休假體系，全面的社會(huì)及商業(yè)保險(xiǎn)。誠邀有志IC事業(yè)的人才加盟共同發(fā)展！
公司提供多樣化福利包：
年終獎(jiǎng)、商業(yè)保險(xiǎn)(給您的寶寶也購買奧)、帶薪年假及帶薪病假、年度體檢、生日蛋糕、結(jié)婚禮金、生育禮金、年度出游、過節(jié)禮金、入職福利。。。。。。如想了解更多，請與我們聯(lián)系。
崗位介紹及要求如下， 有意者請將中文及英文簡歷發(fā)至
hr-xian@scsemicon.com
崗位職責(zé)及要求：
1）數(shù)字后端設(shè)計(jì)工程師ASIC Backend Design Engineer
Responsibilities:
1. Responsible for developing digital designs with emphasis on backend, including Floor-plan, power planning, Place, CTS and Route.
2. Work with Front-end designers to optimize timing/area/power of the design implementation and perform static timing analysis.
3. Optimization and Verification of layout for tape-out (including RC extraction, ECO, DRC, LVS).
4. Power IR drop analysis and optimization, area and parasitic layout optimization, chip size optimization.
5. Static Timing analysis (Prime Time) and setup/hold fix.
6. Formal Verification for equivalence checking (Formality).
7. Generation of fill structures according to technology requirements.
Requirements:
1. Experienced in Synopsys/Cadence automatically physical implementation tools and flows (IC-Compiler/ Astro / SOC-Encounter/ Milky-way/ Star-RCX) is a plus.
3. Experience with one or more scripting languages (Perl, TCL, or Shell) to make reusable automatically flow is a plus.
4. Experience and knowledge about FE design (RTL code, flow) and verification is a plus.
5. Good analytical and debugging skills.
6. Good command of English.
2）可測性設(shè)計(jì)工程師Design for Test Engineer (DFT)
Responsibilities:
1. Participate in SoC level DFT architecture definition.
2. Implement DFT strategy for the SoC chips, cooperating with design team
3. Implement basic DFT schemes, including scan, boundary scan, Mem BIST and Logic BIST.
4. Develop the high coverage and cost effective test patterns.
5. Verify all DFT logics and test patterns with simulation and static timing analysis tool.
6. Support other teams for DFT related problems.
Requirements:
1. Master degree.
2. Basic knowledge of IC design flow, including coding, simulation, verification, synthesis and STA
3. Good understanding of the General DFT methodology such as BIST, SCAN, JTAG and ATPG.
4. Knowledge on and familiar with basic Mentor/ Synopsys DFT flow and tools
5. Proficient in Verilog/VHDL language
6. Be familiar with Shell/TCL/Perl program, or skilled in C program
7. Good English communication skills
8. Self-motivated and good team player
3）數(shù)字電路設(shè)計(jì)工程師Digital Design Engineer
Responsibilities:
1. Responsible for developing complex digital designs with emphasis on Front-End, including Coding, Simulation, Constrain and Synthesis.
2. Responsible for developing high-speed digital designs with Schematic, including schematic, simulation and timing/power/performance optimization.
3. Check the relative block layout implementation.
4. Test-bench and Test-pattern generation to full-cover the relative design.
Requirements:
1. Master or PhD in Microelectronics, Electronic Engineering, or related field, more than 2 years experience, Knowledge.
2. Experience with digital design (Verilog /schematic) and simulation (modelsim, NC-sim, Nanosim) is a plus.
3.Experience in Flash、SRAM and DRAM design is preferred.
4. English language skill in writing and speaking is a must.
4）設(shè)計(jì)驗(yàn)證工程師Design and Functional Verification Engineer (DFV)
Responsibilities:
1. According to the design specification, be responsible for the verification plan and verification objective definition.
2. Test-bench development (modeling, assertions, checkers, monitors, score-board, regressions, coverage), test-case development (sequence, VRAD) and integration.
3. Work with Random Verification methodology(VMM, OVM, UVM, eRM)
4. Work as an independent verification engineers to check the design functionality at SOC module level and chip level.
5. Work as interface with Front-End and Back-End engineer to optimize or review the design architecture and implementation.
6. Verilog or VHDL coding according to design specification or external/internal IP integration.
7. Support the post simulation with gate-level verilog or VHDL net list.
Requirements:
1.Either Bachelor, Master or PhD in Microelectronics, Electronic Engineering, or related field， 2 Years of verification working experience.
2. Experience with Verification language (SPECMAN/E-language, System-Verilog, Vera)
3. Experience with RTL coding and simulators (Modelsim, NC-sim).
4. Basic knowledge of script language (Perl, TCL, C-language and so on)
5. Knowledge about 2G/3G/LTE handset baseband Architecture, ARM, AHB Architecture is a plus.
6. Knowledge about Baseband chip peripheral (USB2.0/USB3.0, SSIC, MIPI) is a plus.
7. Team oriented, love to work in young, international and highly motivated teams.
8. Good command of English
5）集成電路測試工程師（設(shè)計(jì)分析與驗(yàn)證）IC Product Test Engineer (Design Analysis and Verification)
Responsibilities:
1. Design verification and analysis of new Memory products.
2. Simulations and analyses together with responsible circuit designers, correlation of simulation-data versus measurement.
3. Hands on definition, programming and execution of test/test-flows on Memory analysis testers (V93k, HP95k, and Mosaid).
4. Setting up engineering-environments specific to certain tasks and adjust set-up frequently, work with oscilloscopes, TDR, etc.
5. Perform electrical characterization of parameters specified in the data sheet
6. Verify functionality and performance of all DfT-features of a memory product, work with design and production test to identify problems
7. Support of (Field) Application Engineers to identify and analyze problems at the end-customer
8. Definition and specification for product-specific tester-hardware (load-boards, robe-cards, etc.)
Requirements:
1. Either Master or PhD in Computer Science, Electrical Engineering, or related field Experience, Knowledge.
2. Semiconductor device physics, circuit design and requirement ability is basic layout know how.
3. Have UNIX skills and Basic Programming skills (preferably C , Perl)
4. Experience and interest to work in a lab-environment and do hands-on electrical measurements (memory-tester, oscilloscope, pico-probing, etc), setup and debug
5. High frequency measurement know how is desired.
6. Experience in DRAM test and analysis or DRAM tester programming (V93k, HP95k, and Mosaid) is desirable.
7. Highly motivated and engaged， love to find tackle and solve new problems.
8. Good communication and presentation skills.
9. English language skill in writing and speaking is a must.
聯(lián)系方式：
公司地址：西安市高新區(qū)高新六路38號騰飛研發(fā)中心A座4樓
公司電話: 029-88318000 ext.8411（人力資源部）谷小姐
傳真:029-88453299
Email: hr-xian@scsemicon.com
公司網(wǎng)址：http://www.xa
公司的主營業(yè)務(wù)是自有品牌存儲(chǔ)器產(chǎn)品開發(fā)以及先進(jìn)集成電路設(shè)計(jì)測試服務(wù)。華芯自有品牌大容量DRAM芯片及內(nèi)存條，廣泛應(yīng)用于服務(wù)器、平板電腦、高清電視機(jī)頂盒以及工業(yè)控制等領(lǐng)域，產(chǎn)品也遠(yuǎn)銷到大陸外的韓國、歐洲、美國等地。基于世界先進(jìn)工藝的存儲(chǔ)器產(chǎn)品設(shè)計(jì)服務(wù)，已成功給包括日本和臺灣存儲(chǔ)器公司開發(fā)完成多款大容量高速DRAM產(chǎn)品，同時(shí)為國內(nèi)外多個(gè)客戶提供了快速準(zhǔn)確的存儲(chǔ)器測試和失效分析服務(wù)。西安華芯還承擔(dān)有國家“核高基”和“863”計(jì)劃等多個(gè)存儲(chǔ)器領(lǐng)域的研究課題和項(xiàng)目，2014年榮獲國家“國家規(guī)劃布局內(nèi)重點(diǎn)軟件企業(yè)和集成電路設(shè)計(jì)企業(yè)”。
另外，基于公司先進(jìn)豐富的集成電路設(shè)計(jì)測試經(jīng)驗(yàn)和完善嚴(yán)謹(jǐn)?shù)漠a(chǎn)品開發(fā)流程管理和質(zhì)量管理，西安華芯也長期給包括美國公司提供基于先進(jìn)工藝的數(shù)字電路設(shè)計(jì)服務(wù)。
我們提供先進(jìn)的設(shè)計(jì)開發(fā)環(huán)境，優(yōu)厚的薪酬待遇，完善的休假體系，全面的社會(huì)及商業(yè)保險(xiǎn)。誠邀有志IC事業(yè)的人才加盟共同發(fā)展！
公司提供多樣化福利包：
年終獎(jiǎng)、商業(yè)保險(xiǎn)(給您的寶寶也購買奧)、帶薪年假及帶薪病假、年度體檢、生日蛋糕、結(jié)婚禮金、生育禮金、年度出游、過節(jié)禮金、入職福利。。。。。。如想了解更多，請與我們聯(lián)系。
崗位介紹及要求如下， 有意者請將中文及英文簡歷發(fā)至
hr-xian@scsemicon.com
崗位職責(zé)及要求：
1）數(shù)字后端設(shè)計(jì)工程師ASIC Backend Design Engineer
Responsibilities:
1. Responsible for developing digital designs with emphasis on backend, including Floor-plan, power planning, Place, CTS and Route.
2. Work with Front-end designers to optimize timing/area/power of the design implementation and perform static timing analysis.
3. Optimization and Verification of layout for tape-out (including RC extraction, ECO, DRC, LVS).
4. Power IR drop analysis and optimization, area and parasitic layout optimization, chip size optimization.
5. Static Timing analysis (Prime Time) and setup/hold fix.
6. Formal Verification for equivalence checking (Formality).
7. Generation of fill structures according to technology requirements.
Requirements:
1. Experienced in Synopsys/Cadence automatically physical implementation tools and flows (IC-Compiler/ Astro / SOC-Encounter/ Milky-way/ Star-RCX) is a plus.
3. Experience with one or more scripting languages (Perl, TCL, or Shell) to make reusable automatically flow is a plus.
4. Experience and knowledge about FE design (RTL code, flow) and verification is a plus.
5. Good analytical and debugging skills.
6. Good command of English.
2）可測性設(shè)計(jì)工程師Design for Test Engineer (DFT)
Responsibilities:
1. Participate in SoC level DFT architecture definition.
2. Implement DFT strategy for the SoC chips, cooperating with design team
3. Implement basic DFT schemes, including scan, boundary scan, Mem BIST and Logic BIST.
4. Develop the high coverage and cost effective test patterns.
5. Verify all DFT logics and test patterns with simulation and static timing analysis tool.
6. Support other teams for DFT related problems.
Requirements:
1. Master degree.
2. Basic knowledge of IC design flow, including coding, simulation, verification, synthesis and STA
3. Good understanding of the General DFT methodology such as BIST, SCAN, JTAG and ATPG.
4. Knowledge on and familiar with basic Mentor/ Synopsys DFT flow and tools
5. Proficient in Verilog/VHDL language
6. Be familiar with Shell/TCL/Perl program, or skilled in C program
7. Good English communication skills
8. Self-motivated and good team player
3）數(shù)字電路設(shè)計(jì)工程師Digital Design Engineer
Responsibilities:
1. Responsible for developing complex digital designs with emphasis on Front-End, including Coding, Simulation, Constrain and Synthesis.
2. Responsible for developing high-speed digital designs with Schematic, including schematic, simulation and timing/power/performance optimization.
3. Check the relative block layout implementation.
4. Test-bench and Test-pattern generation to full-cover the relative design.
Requirements:
1. Master or PhD in Microelectronics, Electronic Engineering, or related field, more than 2 years experience, Knowledge.
2. Experience with digital design (Verilog /schematic) and simulation (modelsim, NC-sim, Nanosim) is a plus.
3.Experience in Flash、SRAM and DRAM design is preferred.
4. English language skill in writing and speaking is a must.
4）設(shè)計(jì)驗(yàn)證工程師Design and Functional Verification Engineer (DFV)
Responsibilities:
1. According to the design specification, be responsible for the verification plan and verification objective definition.
2. Test-bench development (modeling, assertions, checkers, monitors, score-board, regressions, coverage), test-case development (sequence, VRAD) and integration.
3. Work with Random Verification methodology(VMM, OVM, UVM, eRM)
4. Work as an independent verification engineers to check the design functionality at SOC module level and chip level.
5. Work as interface with Front-End and Back-End engineer to optimize or review the design architecture and implementation.
6. Verilog or VHDL coding according to design specification or external/internal IP integration.
7. Support the post simulation with gate-level verilog or VHDL net list.
Requirements:
1.Either Bachelor, Master or PhD in Microelectronics, Electronic Engineering, or related field， 2 Years of verification working experience.
2. Experience with Verification language (SPECMAN/E-language, System-Verilog, Vera)
3. Experience with RTL coding and simulators (Modelsim, NC-sim).
4. Basic knowledge of script language (Perl, TCL, C-language and so on)
5. Knowledge about 2G/3G/LTE handset baseband Architecture, ARM, AHB Architecture is a plus.
6. Knowledge about Baseband chip peripheral (USB2.0/USB3.0, SSIC, MIPI) is a plus.
7. Team oriented, love to work in young, international and highly motivated teams.
8. Good command of English
5）集成電路測試工程師（設(shè)計(jì)分析與驗(yàn)證）IC Product Test Engineer (Design Analysis and Verification)
Responsibilities:
1. Design verification and analysis of new Memory products.
2. Simulations and analyses together with responsible circuit designers, correlation of simulation-data versus measurement.
3. Hands on definition, programming and execution of test/test-flows on Memory analysis testers (V93k, HP95k, and Mosaid).
4. Setting up engineering-environments specific to certain tasks and adjust set-up frequently, work with oscilloscopes, TDR, etc.
5. Perform electrical characterization of parameters specified in the data sheet
6. Verify functionality and performance of all DfT-features of a memory product, work with design and production test to identify problems
7. Support of (Field) Application Engineers to identify and analyze problems at the end-customer
8. Definition and specification for product-specific tester-hardware (load-boards, robe-cards, etc.)
Requirements:
1. Either Master or PhD in Computer Science, Electrical Engineering, or related field Experience, Knowledge.
2. Semiconductor device physics, circuit design and requirement ability is basic layout know how.
3. Have UNIX skills and Basic Programming skills (preferably C , Perl)
4. Experience and interest to work in a lab-environment and do hands-on electrical measurements (memory-tester, oscilloscope, pico-probing, etc), setup and debug
5. High frequency measurement know how is desired.
6. Experience in DRAM test and analysis or DRAM tester programming (V93k, HP95k, and Mosaid) is desirable.
7. Highly motivated and engaged， love to find tackle and solve new problems.
8. Good communication and presentation skills.
9. English language skill in writing and speaking is a must.
聯(lián)系方式：
公司地址：西安市高新區(qū)高新六路38號騰飛研發(fā)中心A座4樓
公司電話: 029-88318000 ext.8411（人力資源部）谷小姐
傳真:029-88453299
Email: hr-xian@scsemicon.com
公司網(wǎng)址：http://www.xa