一、公司簡介
西安華芯半導(dǎo)體有限公司，創(chuàng)建于2004年初，原為德國英飛凌存儲器事業(yè)部，2006年成為奇夢達(dá)科技有限公司的西安研發(fā)中心。2009年5月被浪潮集團(tuán)山東華芯半導(dǎo)體收購，更名并轉(zhuǎn)制成為國有控股的獨(dú)立公司。公司擁有國內(nèi)、世界同步的集成電路產(chǎn)品設(shè)計(jì)開發(fā)能力，擁有完整先進(jìn)的集成電路設(shè)計(jì)軟硬件平臺以及投資超過一千多萬美元的測試中心。公司現(xiàn)有一百八十多名員工，其中包括10名外籍專家、海外留學(xué)歸國人員和國家“”專家，具有碩士博士學(xué)位人員超過75%。
公司的主營業(yè)務(wù)是自有品牌存儲器產(chǎn)品開發(fā)以及先進(jìn)集成電路設(shè)計(jì)測試服務(wù)。華芯自有品牌大容量DRAM芯片及內(nèi)存條，廣泛應(yīng)用于服務(wù)器、平板電腦、高清電視機(jī)頂盒以及工業(yè)控制等領(lǐng)域，產(chǎn)品也遠(yuǎn)銷到大陸外的韓國、歐洲、美國等地?；谑澜缦冗M(jìn)工藝的存儲器產(chǎn)品設(shè)計(jì)服務(wù)，已成功給包括日本和臺灣存儲器公司開發(fā)完成多款大容量高速DRAM產(chǎn)品，同時為國內(nèi)外多個客戶提供了快速準(zhǔn)確的存儲器測試和失效分析服務(wù)。西安華芯還承擔(dān)有國家“核高基”和“863”計(jì)劃等多個存儲器領(lǐng)域的研究課題和項(xiàng)目，2014年榮獲國家“國家規(guī)劃布局內(nèi)重點(diǎn)軟件企業(yè)和集成電路設(shè)計(jì)企業(yè)”。
另外，基于公司先進(jìn)豐富的集成電路設(shè)計(jì)測試經(jīng)驗(yàn)和完善嚴(yán)謹(jǐn)?shù)漠a(chǎn)品開發(fā)流程管理和質(zhì)量管理，西安華芯也長期給包括美國公司提供基于先進(jìn)工藝的數(shù)字電路設(shè)計(jì)服務(wù)。
我們提供先進(jìn)的設(shè)計(jì)開發(fā)環(huán)境，優(yōu)厚的薪酬待遇，完善的休假體系，全面的社會及商業(yè)保險。誠邀有志IC事業(yè)的人才加盟共同發(fā)展!
二、招聘信息
1)數(shù)字后端設(shè)計(jì)工程師ASIC Backend Design Engineer
Responsibilities:
1. Responsible for developing digital designs with emphasis on backend, including Floor-plan, power planning, Place, CTS and Route.
2. Work with Front-end designers to optimize timing/area/power of the design implementation and perform static timing analysis.
3. Optimization and Verification of layout for tape-out (including RC extraction, ECO, DRC, LVS).
4. Power IR drop analysis and optimization, area and parasitic layout optimization, chip size optimization.
5. Static Timing analysis (Prime Time) and setup/hold fix.
6. Formal Verification for equivalence checking (Formality).
7. Generation of fill structures according to technology requirements.
2)Flash電路設(shè)計(jì)工程師Flash Memory Circuit Design Engineer
Responsibility:
1. Design and simulation of Flash memory at deep sub-micron process node including row and column decoding, read/program/erase control circuits and read sense amplifier etc.
2. Verify the function and performance of FLASH memory at block-level and full-chip level.
3. Floor-planning FLASH chip architecture.
4. Work closely with layout engineer, provide layout guide line, and check the layout quality.
5. Analysis chip's performance and debug chip's problems at silicon.
3)可測性設(shè)計(jì)工程師Design for Test Engineer (DFT)
Responsibilities:
1. Participate in SoC level DFT architecture definition.
2. Implement DFT strategy for the SoC chips, cooperating with design team.
3. Implement basic DFT schemes, including scan, boundary scan, Mem BIST and Logic BIST.
4. Develop the high coverage and cost effective test patterns.
5. Verify all DFT logics and test patterns with simulation and static timing analysis tool.
6. Support other teams for DFT related problems.
4)數(shù)字電路設(shè)計(jì)工程師Digital Design Engineer
Responsibilities:
1. Responsible for developing complex digital designs with emphasis on Front-End, including Coding, Simulation, Constrain and Synthesis.
2. Responsible for developing high-speed digital designs with Schematic, including schematic, simulation and timing/power/performance optimization.
3. Check the relative block layout implementation.
4. Test-bench and Test-pattern generation to full-cover the relative design.
5)模擬電路設(shè)計(jì)工程師Analog IC Design Engineer
Responsibilities:
1. Design high-performance analog and mixed-signal circuits for consumer electronics applications.
2. Check layout and physical implementation of the relative Block.
3. Circuit optimization and verification by simulations using HSPICE like simulation tools as well as event driven simulators
4. Other responsibilities include supporting other groups in the test, qualification and release to production.
三、福利待遇
N個月年終獎、五險一金之外的商業(yè)保險(給您的寶寶也購買奧)、12天帶薪年假及14天帶薪病假、年度體檢、生日蛋糕、結(jié)婚禮金、生育禮金、年度出游、過節(jié)禮金、報銷入職機(jī)票并提供7天快捷酒店費(fèi)用。。。。。。
四、聯(lián)系方式
公司地址：西安市高新區(qū)高新六路38號騰飛研發(fā)中心A座4樓
公司電話：029-88318000 ext.8411(人力資源部)谷小姐
傳真：029-88453299
Email：有意者請將中文及英文簡歷發(fā)至hr-xian@scsemicon.com
西安華芯半導(dǎo)體有限公司，創(chuàng)建于2004年初，原為德國英飛凌存儲器事業(yè)部，2006年成為奇夢達(dá)科技有限公司的西安研發(fā)中心。2009年5月被浪潮集團(tuán)山東華芯半導(dǎo)體收購，更名并轉(zhuǎn)制成為國有控股的獨(dú)立公司。公司擁有國內(nèi)、世界同步的集成電路產(chǎn)品設(shè)計(jì)開發(fā)能力，擁有完整先進(jìn)的集成電路設(shè)計(jì)軟硬件平臺以及投資超過一千多萬美元的測試中心。公司現(xiàn)有一百八十多名員工，其中包括10名外籍專家、海外留學(xué)歸國人員和國家“”專家，具有碩士博士學(xué)位人員超過75%。
公司的主營業(yè)務(wù)是自有品牌存儲器產(chǎn)品開發(fā)以及先進(jìn)集成電路設(shè)計(jì)測試服務(wù)。華芯自有品牌大容量DRAM芯片及內(nèi)存條，廣泛應(yīng)用于服務(wù)器、平板電腦、高清電視機(jī)頂盒以及工業(yè)控制等領(lǐng)域，產(chǎn)品也遠(yuǎn)銷到大陸外的韓國、歐洲、美國等地?；谑澜缦冗M(jìn)工藝的存儲器產(chǎn)品設(shè)計(jì)服務(wù)，已成功給包括日本和臺灣存儲器公司開發(fā)完成多款大容量高速DRAM產(chǎn)品，同時為國內(nèi)外多個客戶提供了快速準(zhǔn)確的存儲器測試和失效分析服務(wù)。西安華芯還承擔(dān)有國家“核高基”和“863”計(jì)劃等多個存儲器領(lǐng)域的研究課題和項(xiàng)目，2014年榮獲國家“國家規(guī)劃布局內(nèi)重點(diǎn)軟件企業(yè)和集成電路設(shè)計(jì)企業(yè)”。
另外，基于公司先進(jìn)豐富的集成電路設(shè)計(jì)測試經(jīng)驗(yàn)和完善嚴(yán)謹(jǐn)?shù)漠a(chǎn)品開發(fā)流程管理和質(zhì)量管理，西安華芯也長期給包括美國公司提供基于先進(jìn)工藝的數(shù)字電路設(shè)計(jì)服務(wù)。
我們提供先進(jìn)的設(shè)計(jì)開發(fā)環(huán)境，優(yōu)厚的薪酬待遇，完善的休假體系，全面的社會及商業(yè)保險。誠邀有志IC事業(yè)的人才加盟共同發(fā)展!
二、招聘信息
1)數(shù)字后端設(shè)計(jì)工程師ASIC Backend Design Engineer
Responsibilities:
1. Responsible for developing digital designs with emphasis on backend, including Floor-plan, power planning, Place, CTS and Route.
2. Work with Front-end designers to optimize timing/area/power of the design implementation and perform static timing analysis.
3. Optimization and Verification of layout for tape-out (including RC extraction, ECO, DRC, LVS).
4. Power IR drop analysis and optimization, area and parasitic layout optimization, chip size optimization.
5. Static Timing analysis (Prime Time) and setup/hold fix.
6. Formal Verification for equivalence checking (Formality).
7. Generation of fill structures according to technology requirements.
2)Flash電路設(shè)計(jì)工程師Flash Memory Circuit Design Engineer
Responsibility:
1. Design and simulation of Flash memory at deep sub-micron process node including row and column decoding, read/program/erase control circuits and read sense amplifier etc.
2. Verify the function and performance of FLASH memory at block-level and full-chip level.
3. Floor-planning FLASH chip architecture.
4. Work closely with layout engineer, provide layout guide line, and check the layout quality.
5. Analysis chip's performance and debug chip's problems at silicon.
3)可測性設(shè)計(jì)工程師Design for Test Engineer (DFT)
Responsibilities:
1. Participate in SoC level DFT architecture definition.
2. Implement DFT strategy for the SoC chips, cooperating with design team.
3. Implement basic DFT schemes, including scan, boundary scan, Mem BIST and Logic BIST.
4. Develop the high coverage and cost effective test patterns.
5. Verify all DFT logics and test patterns with simulation and static timing analysis tool.
6. Support other teams for DFT related problems.
4)數(shù)字電路設(shè)計(jì)工程師Digital Design Engineer
Responsibilities:
1. Responsible for developing complex digital designs with emphasis on Front-End, including Coding, Simulation, Constrain and Synthesis.
2. Responsible for developing high-speed digital designs with Schematic, including schematic, simulation and timing/power/performance optimization.
3. Check the relative block layout implementation.
4. Test-bench and Test-pattern generation to full-cover the relative design.
5)模擬電路設(shè)計(jì)工程師Analog IC Design Engineer
Responsibilities:
1. Design high-performance analog and mixed-signal circuits for consumer electronics applications.
2. Check layout and physical implementation of the relative Block.
3. Circuit optimization and verification by simulations using HSPICE like simulation tools as well as event driven simulators
4. Other responsibilities include supporting other groups in the test, qualification and release to production.
三、福利待遇
N個月年終獎、五險一金之外的商業(yè)保險(給您的寶寶也購買奧)、12天帶薪年假及14天帶薪病假、年度體檢、生日蛋糕、結(jié)婚禮金、生育禮金、年度出游、過節(jié)禮金、報銷入職機(jī)票并提供7天快捷酒店費(fèi)用。。。。。。
四、聯(lián)系方式
公司地址：西安市高新區(qū)高新六路38號騰飛研發(fā)中心A座4樓
公司電話：029-88318000 ext.8411(人力資源部)谷小姐
傳真：029-88453299
Email：有意者請將中文及英文簡歷發(fā)至hr-xian@scsemicon.com