這篇《飛兆半導(dǎo)體2014北京校園招聘ASIC Digital Design Engineer》是為大家整理的，希望對大家有所幫助。以下信息僅供參考！??！
飛兆半導(dǎo)體公司(美國紐約股票交易所股票代號：FCS)總部位于美國加州圣何塞，專為功率及便攜設(shè)計提供高能效、易于應(yīng)用及高增值的半導(dǎo)體解決方案。飛兆半導(dǎo)體是目前世界上在高性能電源、接口，模擬與混合信號、邏輯線路光電子及可配置產(chǎn)品方面最主要的供應(yīng)商，集獨立設(shè)計、制造和營銷于一體。
飛兆半導(dǎo)體在全球設(shè)有9 家研發(fā)中心，其中在中國的研發(fā)中心位于北京和上海。在全球設(shè)有8家工廠，其中4家位于亞太地區(qū)。 6個地區(qū)銷售總部，并于17個國家和地區(qū)設(shè)有45個直銷據(jù)點，其終端市場應(yīng)用包括：工業(yè)應(yīng)用、消費電子、通信、計算機(jī)和顯示器，以及汽車應(yīng)用等。
招聘職位：ASIC Digital Design Engineer
工作地點：北京
專業(yè)： 微電子，電子工程等相關(guān)專業(yè)
學(xué)歷：碩士
Job Title: ASIC digital design engineer
Location: Beijing
Responsibility
In charge of digital design and verification in Mix-signal chip
Take part in all ASIC design flow including Coding, Verification, Synthesis, STA, Place and Route
Perform functional verification of designs on block and AMS level.
Perform pre- and post-layout timing closure
Perform physical design including floor planning, timing closure, place&route, physical verification etc.
Develop and improve design quality like area, power, timing and ATPG coverage
Requirement
Master Degree in Micro-electronics, electronics engineering or related;
Experience in ASIC design flow (logic synthesis, STA, formality check,
P&R, Design for Test), familiar with verilog and the usage of related EDA tools
Experience with design for verification (assertion based design strategies, code coverage, functional coverage, test plan, gate-level simulation, back-annotation etc.). Mixed-signal verification background or familiar with system verilog,
C++ would be an added advantage.
Understanding of synthesis flow
Familiar with STA skills
Hands on experience with formal verification tools such as LEC and/or formality
Familiar with Back-End EDA tools (synopsys,cadence,magma)
Familiar with Linux Environment
Ability to build new EDA-methodology-flow using perl, tcl and shell programming would be an added advantage
Good communication skills, strong interpersonal skills and the flexibility Dedicated, hard working and good team player
2014 Fairchild校園招聘流程：
1.發(fā)布校園招聘信息：
2. 投遞簡歷：recruit@fairchildsemi.com
(請在標(biāo)題中注明 畢業(yè)院校 +專業(yè)+ 應(yīng)聘職位+ 期望工作地點)
3. 簡歷篩選
4. 邀請參加Fairchild Seminar
5. 筆試
6. 面試
7. Offer
2014 Fairchild校園招聘之Seminar安排:
(具體時間&地點將分別通知投遞簡歷并被邀請的同學(xué))
9月23日，上海
9月27日，成都
10月9日，北京
飛兆半導(dǎo)體公司(美國紐約股票交易所股票代號：FCS)總部位于美國加州圣何塞，專為功率及便攜設(shè)計提供高能效、易于應(yīng)用及高增值的半導(dǎo)體解決方案。飛兆半導(dǎo)體是目前世界上在高性能電源、接口，模擬與混合信號、邏輯線路光電子及可配置產(chǎn)品方面最主要的供應(yīng)商，集獨立設(shè)計、制造和營銷于一體。
飛兆半導(dǎo)體在全球設(shè)有9 家研發(fā)中心，其中在中國的研發(fā)中心位于北京和上海。在全球設(shè)有8家工廠，其中4家位于亞太地區(qū)。 6個地區(qū)銷售總部，并于17個國家和地區(qū)設(shè)有45個直銷據(jù)點，其終端市場應(yīng)用包括：工業(yè)應(yīng)用、消費電子、通信、計算機(jī)和顯示器，以及汽車應(yīng)用等。
招聘職位：ASIC Digital Design Engineer
工作地點：北京
專業(yè)： 微電子，電子工程等相關(guān)專業(yè)
學(xué)歷：碩士
Job Title: ASIC digital design engineer
Location: Beijing
Responsibility
In charge of digital design and verification in Mix-signal chip
Take part in all ASIC design flow including Coding, Verification, Synthesis, STA, Place and Route
Perform functional verification of designs on block and AMS level.
Perform pre- and post-layout timing closure
Perform physical design including floor planning, timing closure, place&route, physical verification etc.
Develop and improve design quality like area, power, timing and ATPG coverage
Requirement
Master Degree in Micro-electronics, electronics engineering or related;
Experience in ASIC design flow (logic synthesis, STA, formality check,
P&R, Design for Test), familiar with verilog and the usage of related EDA tools
Experience with design for verification (assertion based design strategies, code coverage, functional coverage, test plan, gate-level simulation, back-annotation etc.). Mixed-signal verification background or familiar with system verilog,
C++ would be an added advantage.
Understanding of synthesis flow
Familiar with STA skills
Hands on experience with formal verification tools such as LEC and/or formality
Familiar with Back-End EDA tools (synopsys,cadence,magma)
Familiar with Linux Environment
Ability to build new EDA-methodology-flow using perl, tcl and shell programming would be an added advantage
Good communication skills, strong interpersonal skills and the flexibility Dedicated, hard working and good team player
2014 Fairchild校園招聘流程：
1.發(fā)布校園招聘信息：
2. 投遞簡歷：recruit@fairchildsemi.com
(請在標(biāo)題中注明 畢業(yè)院校 +專業(yè)+ 應(yīng)聘職位+ 期望工作地點)
3. 簡歷篩選
4. 邀請參加Fairchild Seminar
5. 筆試
6. 面試
7. Offer
2014 Fairchild校園招聘之Seminar安排:
(具體時間&地點將分別通知投遞簡歷并被邀請的同學(xué))
9月23日，上海
9月27日，成都
10月9日，北京