IBM芯片設(shè)計(jì)中心招聘流程
【名稱】
IBM芯片設(shè)計(jì)中心(CDC, Chip Design Center)
【投簡(jiǎn)歷方式】
統(tǒng)一通過51job進(jìn)行收集，請(qǐng)學(xué)生們
(1) 登陸http://2012ibmcampus.51job.com/
(2) 點(diǎn)擊"2012 Position" -> "Apply Now"
(3) 進(jìn)入下一個(gè)頁面后，點(diǎn)擊Apply Now -> CSTL
(4) 進(jìn)入下一個(gè)頁面后，點(diǎn)擊"Chip Design Engineer"后方的"Apply"，完成簡(jiǎn)歷的投遞
注：a. 為了便于我們收集簡(jiǎn)歷，請(qǐng)將申請(qǐng)的第一職位選為"Chip Design Engineer"
b. 我們部門在北京上海無錫都設(shè)有team，員工可以根據(jù)自身需求，自由選擇工作地點(diǎn)
。
c. 上海交大的簡(jiǎn)歷收集截止日期是 9/23（下周五）
【面試流程】
a. 我們將在9月23日之后安排面試。
b. 1面、2面均通過電話方式進(jìn)行通知，請(qǐng)同學(xué)們保持手機(jī)暢通。
c. 1面一般不需要特別準(zhǔn)備，但是2面需要同學(xué)們準(zhǔn)備15分鐘的PPT，主題不做限制，
可以簡(jiǎn)單介紹曾經(jīng)參與過的項(xiàng)目或任何可以幫助面試官更好了解你的材料。
d. 通知進(jìn)入2面到開始2面的間隔可能會(huì)很短，有些同學(xué)或許來不及準(zhǔn)備PPT，所以建
議每個(gè)參加面試的同學(xué)事先都將PPT準(zhǔn)備好。
e. 對(duì)于順利通過2面的同學(xué)，我們通常會(huì)在面試結(jié)束后的2周內(nèi)，給出回音。
重要申明：本次招聘活動(dòng)是IBM針對(duì)芯片相關(guān)學(xué)生所增加的專場(chǎng)，與IBM正式的校園招聘活
動(dòng)不沖突。
*——*——*——*——*——*——*——*——*——*——*——*——*——*——*
IBM CDC 校園招聘 芯片設(shè)計(jì)工程師職位需求
Job Scope:
IBM Chip Design Engineers are working on cutting edge SoC (System on a Chip),
ASIC, High Performance Processor, Chipset, Digital/Analog and Mix-signal Circu
it IP design for our clients inside and outside of IBM. By employing the indus
try leading tools, state of the art methodology, and innovative semiconductor
technologies ranging from 90nm to 22nm and beyond, you will be participating i
n the development of end to end solutions including architecture design and pe
rformance analysis/tuning, front-end logic design and verification, back-end i
mplementation and optimization, circuit IP design, package and electrical desi
gn, EDA & Methodology development and deployment, as well as Chip hardware val
idation.
Key Attributes:
1. CS/EE or background in digital or analog Chip Design related areas
2. Research and development experience in one or more of the following areas:
* Architectural design, analysis, and optimization
* Proficient in Verilog/VHDL, and well conversant with programming and scri
pt languages
* Digital logic implementation and verification on the basis of the target
system specification
* SoC design methodology: Knowledge of SoC integration, modeling and verifi
cation at different abstract level
* ASIC Back-end design methodology: Knowledge of synthesis, timing, DFT, fl
oorplanning, physical design, signal/power integrity, packaging, and other bac
k-end activities.
* Electronic Design Automation algorithm, tool, and methodology development
* Experience/knowledge in the field of Analog and mixed-signal IP design, t
est and evaluation with Bulk CMOS, BiCMOS, SiGe, or SOI technologies.
* Good software background and strong C/C skill is a significant plus.
3. Experience in one or some of the application domains, will be a plus
* High performance computing (servers) System, Processor, Chipset and ASICs
* Communication, Networking and wireless applications
* Digital signal processing and RISC Processor architecture
* Digital Media, Audio/Video Graphic and Gaming processing
* Consumer Electronics applications
* High Speed Interface/Serdes applications
* Other emerging technology and industry areas
4. Good English/communication skill and willingness to work with a global team
. Skill of other languages will be a good plus.
5. Good learning competency and be able to work in diverse areas in a flexible
environment
【名稱】
IBM芯片設(shè)計(jì)中心(CDC, Chip Design Center)
【投簡(jiǎn)歷方式】
統(tǒng)一通過51job進(jìn)行收集，請(qǐng)學(xué)生們
(1) 登陸http://2012ibmcampus.51job.com/
(2) 點(diǎn)擊"2012 Position" -> "Apply Now"
(3) 進(jìn)入下一個(gè)頁面后，點(diǎn)擊Apply Now -> CSTL
(4) 進(jìn)入下一個(gè)頁面后，點(diǎn)擊"Chip Design Engineer"后方的"Apply"，完成簡(jiǎn)歷的投遞
注：a. 為了便于我們收集簡(jiǎn)歷，請(qǐng)將申請(qǐng)的第一職位選為"Chip Design Engineer"
b. 我們部門在北京上海無錫都設(shè)有team，員工可以根據(jù)自身需求，自由選擇工作地點(diǎn)
。
c. 上海交大的簡(jiǎn)歷收集截止日期是 9/23（下周五）
【面試流程】
a. 我們將在9月23日之后安排面試。
b. 1面、2面均通過電話方式進(jìn)行通知，請(qǐng)同學(xué)們保持手機(jī)暢通。
c. 1面一般不需要特別準(zhǔn)備，但是2面需要同學(xué)們準(zhǔn)備15分鐘的PPT，主題不做限制，
可以簡(jiǎn)單介紹曾經(jīng)參與過的項(xiàng)目或任何可以幫助面試官更好了解你的材料。
d. 通知進(jìn)入2面到開始2面的間隔可能會(huì)很短，有些同學(xué)或許來不及準(zhǔn)備PPT，所以建
議每個(gè)參加面試的同學(xué)事先都將PPT準(zhǔn)備好。
e. 對(duì)于順利通過2面的同學(xué)，我們通常會(huì)在面試結(jié)束后的2周內(nèi)，給出回音。
重要申明：本次招聘活動(dòng)是IBM針對(duì)芯片相關(guān)學(xué)生所增加的專場(chǎng)，與IBM正式的校園招聘活
動(dòng)不沖突。
*——*——*——*——*——*——*——*——*——*——*——*——*——*——*
IBM CDC 校園招聘 芯片設(shè)計(jì)工程師職位需求
Job Scope:
IBM Chip Design Engineers are working on cutting edge SoC (System on a Chip),
ASIC, High Performance Processor, Chipset, Digital/Analog and Mix-signal Circu
it IP design for our clients inside and outside of IBM. By employing the indus
try leading tools, state of the art methodology, and innovative semiconductor
technologies ranging from 90nm to 22nm and beyond, you will be participating i
n the development of end to end solutions including architecture design and pe
rformance analysis/tuning, front-end logic design and verification, back-end i
mplementation and optimization, circuit IP design, package and electrical desi
gn, EDA & Methodology development and deployment, as well as Chip hardware val
idation.
Key Attributes:
1. CS/EE or background in digital or analog Chip Design related areas
2. Research and development experience in one or more of the following areas:
* Architectural design, analysis, and optimization
* Proficient in Verilog/VHDL, and well conversant with programming and scri
pt languages
* Digital logic implementation and verification on the basis of the target
system specification
* SoC design methodology: Knowledge of SoC integration, modeling and verifi
cation at different abstract level
* ASIC Back-end design methodology: Knowledge of synthesis, timing, DFT, fl
oorplanning, physical design, signal/power integrity, packaging, and other bac
k-end activities.
* Electronic Design Automation algorithm, tool, and methodology development
* Experience/knowledge in the field of Analog and mixed-signal IP design, t
est and evaluation with Bulk CMOS, BiCMOS, SiGe, or SOI technologies.
* Good software background and strong C/C skill is a significant plus.
3. Experience in one or some of the application domains, will be a plus
* High performance computing (servers) System, Processor, Chipset and ASICs
* Communication, Networking and wireless applications
* Digital signal processing and RISC Processor architecture
* Digital Media, Audio/Video Graphic and Gaming processing
* Consumer Electronics applications
* High Speed Interface/Serdes applications
* Other emerging technology and industry areas
4. Good English/communication skill and willingness to work with a global team
. Skill of other languages will be a good plus.
5. Good learning competency and be able to work in diverse areas in a flexible
environment