如果有符合條件并感興趣的，請mail 聯(lián)系我：xi.huang@panovel.com
招聘職位對經(jīng)驗要求比較高，如果有過類似的項目經(jīng)驗并且具備一定條件的也可以考慮。
公司網(wǎng)址：www.panovel.com
職位名稱：資深A(yù)SIC驗證工程師
Position title: Senior ASIC Verification Engineer
1． Responsibilities:
1) Working within an ASIC design team to develop reusable block-level and A
SIC testbenches using high-level verification
language (System Verilog).
2) Develop new ASIC verification environments to support ASIC development.
3) Review RTL architectural and implementation specifications.
4) Create stimulus drivers, monitors, dataflow models, and test plans to ve
rify function and performance of advanced SOC
ASICs.
5) Define and implement code/functional coverage plans.
6) Develop testing and regression methodologies for new verification flow.
7) Incorporate reusability into all aspects of the verification environment
.
8) Develop/maintain/enhance environment tools/scripts/makefiles.
2． Qualification:
1) Minimum of 3 years ASIC verification experience in a product development
environment with proven ASIC design
verification skills
2) Experience in using event-driven simulators like VCS
3) Fluent in Verilog for design verification
4) Experience in writing testbench using System Verilog
5) Knowledge of peripheral IP intergration (PCI, USB2.0, PCI)
6) Knowledge of AMBA/AHB/DMA
7) Experience with one or more scripting languages: Perl, TCL, Shell
8) Superior debugging skills for large ASIC designs
9) Strong written and verbal communication skills
3． Required Degree: MS
Preferred Major: Electrical Engineering or related discipline
職位名稱：SoC ASIC 設(shè)計工程師
1． 職責(zé)
(1) 在UWB片上系統(tǒng)(SoC)上集成ARM處理器和AMBA總線；
(2) 設(shè)計DMA；
(3) 實現(xiàn)MAC功能，如排隊管理；
(4) 與‘物理層ASIC工作組’和‘固件工作組’合作完成‘物理層-MAC’接口。
2． 資格
(1) 具有SoC設(shè)計的豐富經(jīng)驗；
(2) 具有ASIC設(shè)計流程的豐富；
(3) 具有ARM/AMBA集成的經(jīng)驗；
(4) 具有DMA設(shè)計經(jīng)驗；
(5) 在復(fù)雜FIFO管理方面有經(jīng)驗。
3． 優(yōu)先考慮:
有以下經(jīng)驗者：ARM 集成，AMBA總線，DMA和MAC；碩士或以上學(xué)位。
招聘職位對經(jīng)驗要求比較高，如果有過類似的項目經(jīng)驗并且具備一定條件的也可以考慮。
公司網(wǎng)址：www.panovel.com
職位名稱：資深A(yù)SIC驗證工程師
Position title: Senior ASIC Verification Engineer
1． Responsibilities:
1) Working within an ASIC design team to develop reusable block-level and A
SIC testbenches using high-level verification
language (System Verilog).
2) Develop new ASIC verification environments to support ASIC development.
3) Review RTL architectural and implementation specifications.
4) Create stimulus drivers, monitors, dataflow models, and test plans to ve
rify function and performance of advanced SOC
ASICs.
5) Define and implement code/functional coverage plans.
6) Develop testing and regression methodologies for new verification flow.
7) Incorporate reusability into all aspects of the verification environment
.
8) Develop/maintain/enhance environment tools/scripts/makefiles.
2． Qualification:
1) Minimum of 3 years ASIC verification experience in a product development
environment with proven ASIC design
verification skills
2) Experience in using event-driven simulators like VCS
3) Fluent in Verilog for design verification
4) Experience in writing testbench using System Verilog
5) Knowledge of peripheral IP intergration (PCI, USB2.0, PCI)
6) Knowledge of AMBA/AHB/DMA
7) Experience with one or more scripting languages: Perl, TCL, Shell
8) Superior debugging skills for large ASIC designs
9) Strong written and verbal communication skills
3． Required Degree: MS
Preferred Major: Electrical Engineering or related discipline
職位名稱：SoC ASIC 設(shè)計工程師
1． 職責(zé)
(1) 在UWB片上系統(tǒng)(SoC)上集成ARM處理器和AMBA總線；
(2) 設(shè)計DMA；
(3) 實現(xiàn)MAC功能，如排隊管理；
(4) 與‘物理層ASIC工作組’和‘固件工作組’合作完成‘物理層-MAC’接口。
2． 資格
(1) 具有SoC設(shè)計的豐富經(jīng)驗；
(2) 具有ASIC設(shè)計流程的豐富；
(3) 具有ARM/AMBA集成的經(jīng)驗；
(4) 具有DMA設(shè)計經(jīng)驗；
(5) 在復(fù)雜FIFO管理方面有經(jīng)驗。
3． 優(yōu)先考慮:
有以下經(jīng)驗者：ARM 集成，AMBA總線，DMA和MAC；碩士或以上學(xué)位。